As is well known, a typical Design-for-Test (“DFT”) technique for a digital electronic circuit (“DCCT”) entails providing a “back-door” mechanism to load and unload data storage cells (for example, flip-flops) of the DCCT. Such a “back-door” mechanism, also referred to herein as a “scan DFT mechanism” simplifies (a) the application of stimuli to circuit elements and storage cells in the DCCT; and (b) the observation of resulting responses from the circuit elements and storage cells in the DCCT. As is also well known, a scan DFT mechanism is implemented in a DCCT during its physical design to provide a scan-mechanism-enabled DCCT by: (a) replacing storage cells in the DCCT with corresponding storage cells having a back-door mechanism (i.e., a scan DFT mechanism); and (b) interconnecting them in a test network to dedicated test input and output pins.
DCCTs are typically designed using standard cells, which standard cells include circuit elements such as logic gates (i.e., AND, OR, NOT, etc.) and data storage cells (also known as memory cells) such as, for example and without limitation, flip-flops, data latches or similar elements. In FIG. 1, each square represents a standard cell, and each dark square represents a data storage cell that has been replaced with an equivalent cell, i.e., a data storage cell having a back-door mechanism (i.e., a scan DFT mechanism). A data storage cell (for example, a flip-flop) having a back-door mechanism (i.e., a scan DFT mechanism) will be referred to herein as a “scan cell.” As is well known, Automatic Test Pattern Generation (“ATPG”) tools (typically software tools) use the scan DFT mechanism in a scan-mechanism-enabled DCCT to automatically generate manufacturing tests for the DCCT.
Each DCCT is composed of functional blocks that are assembled together hierarchically. This defines its logical hierarchy. Before it is cast into silicon, each DCCT has to be synthesized into a network of standard-cells where each such standard-cell is placed in a two-dimensional grid, and their pins are interconnected by wires. This process is called physical design or Place-and-Route. Physical design is also done hierarchically to mitigate performance and capacity limitations of Place-and-Route software tools. The physical hierarchy of a DCCT is usually much flatter than its logical hierarchy. For example up to ten levels of logical hierarchy is common in modern DCCTs while only two levels of physical hierarchy is usually sufficient.
A serial scan (“SS”) DFT technique is typically used in the prior art to provide a back-door mechanism. A typical prior art SS DFT technique involves creating a scan cell for each flip-flop in the DCCT by adding a multiplexor to the data input port of each flip-flop, and interconnecting all the flip-flops in the DCCT, under a test mode, to operate as one or more shift registers. For example, in a test mode, all the flip-flops in the DCCT may be connected in cascade to operate as a single shift register. This is illustrated in FIG. 2 where SI and SO pins indicate scan input test signals and scan output test signals, respectively. Arbitrary test stimuli (i.e., test patterns) can be shifted into the SI pin, and arbitrary responses can be shifted out of the SO pin. As is well known, to reduce cost, the area occupied by circuitry added to a DCCT to implement a DFT technique ought to be reduced. As such, a main advantage of a prior art SS DFT technique is the relatively small area occupied by the circuitry added to implement the SS DFT technique. In particular, the SS DFT technique is ideal if all the flip-flops in a DCCT need to be loaded with stimulus data and response data unloaded for comparison with expected values for each test pattern. However, for large DCCTs, the SS DFT technique is not ideal since only a small fraction of the flip-flops in the DCCT needs to be loaded or unloaded in most test patterns. Since all the flip-flops configured as a shift register in an SS DFT technique need to be clocked in every cycle of a load or unload operation, DCCTs implementing the SS DFT technique dissipate large amounts of power during manufacturing tests, which large amounts of power may degrade or even damage the DCCTs, thereby negatively affecting their reliability or performance.
In contrast to the prior art SS DFT technique, a prior art random access scan (“RAS”) DFT technique involves: (a) creating an RAS flip-flop to replace each flip-flop in the DCCT (where an RAS flip-flop is a regular flip-flop with a data input multiplexor and one or more enable inputs (i.e., a demultiplexor)); and (b) adding global multiplexing logic to the DCCT to enable loading or unloading one flip-flop at a time under a test mode. The RAS DFT technique is illustrated in FIG. 3 where the global multiplexing logic comprises multiplexors (i.e., multiplexor logic circuitry) and demultiplexors (i.e., demultiplexor logic circuitry) surrounding the DCCT. As shown in FIG. 3, ADDRESS represents a multi-bit address signal used to select one of the demultiplexors and one corresponding multiplexor so that only one flip-flop is connected between SI and SO signal pins for loading and unloading data, respectively, for that flip-flop. As a result, an arbitrary test stimulus can be applied to each flip-flop from the SI pin and an arbitrary response can be observed from each flip-flop at the SO pin, one flip-flop at a time. Since only flip-flops relevant to a test pattern are loaded or unloaded, leaving others alone, the prior art RAS DFT technique provides the lowest possible power dissipation during manufacturing tests. Typically, as shown in FIG. 3, the multi-bit address signal (ADDRESS), the scan input (SI) and the scan output (SO) are serially accessed to minimize the number of test pins. Most prior art RAS DFT techniques use a two-dimensional (2-D) physical grid layout to address each and every storage element (for example, flip-flop) in a DCCT. This is illustrated in FIG. 4. As indicated in FIG. 4, the scan input is broadcast to all flip-flops in the logic array, and each flip-flop gets a row select and a column select signal, which row select and column select signals act as distributed demultiplexor signals. In addition, all flip-flops, except the selected flip-flop, generate a logical “0” to scan output OR logic, which scan output OR logic thereby acts as a distributed multiplexor. Note that decoded row address, decoded column address, broadcast scan input, and row scan output buses traverse the DCCT. Hence, prior art 2-D RAS DFT techniques increase DCCT cost due to high wiring area overhead. For example, a 2-D grid containing 256 RAS flip-flops will have 4 bit row addresses and 4 bit column addresses, yielding 16 row and column select lines (16×16=256). Typically, as shown in FIG. 4, the row address (RAD), the column address (CAD), the scan input (SI) and the scan output (SO) are serially accessed to minimize the number of test pins. FIG. 5 illustrates a 2-D grid where each rectangular slot represents a sequential cell such as a flip-flop in the DCCT. As one can understand from FIG. 5, in this layout, there are 16 long wires each in the horizontal and vertical directions, totaling 32 long wires.
In some prior art RAS DFT techniques, a 2-D (i.e., row and column) address of a sequential element to be controlled or observed is serially shifted into (row and column) address registers that, in turn, drive (row and column) decoders to reduce test pin count. This is problematic since it increases the test application time (“TAT”) when test patterns need to load or unload a large number of sequential elements in the DCCT.
System-On-Chip (SOC) circuits are typically separated into several physical blocks, each of which may represent a DCCT, and each of which physical blocks is separately implemented to overcome capacity limitations of Place-and-Route software tools for physical design implementations. Prior art RAS DFT techniques have been proposed to localize 2-D physical grid layouts to each physical block of the SOC, however, this approach does not effectively mitigate the high wiring area overhead of prior art 2-D RAS DFT techniques for large physical design blocks.
Some prior art RAS DFT techniques use test compression techniques that are implemented using Multiple Input Signature Registers (MISR). However, instead of comparing the output response of a manufactured DCCT against expected individual values from simulation for each test, only a final, compressed response signature, obtained after applying all tests, is compared against an expected signature calculated by circuit simulations. This is done to reduce test application time (“TAT”), and test pattern data volume (TDV) that needs to be handled outside of the DCCT. In digital circuits, a logic value on a signal line would be either 0 or 1. However, in situations where a value cannot be determined as 0 or 1, a symbolic value X is assigned, with the restriction that it is either 0 or 1. ATPG tools use zero delay simulation, and therefore, use the unknown (or unpredictable) value X to model race and hazard signal paths, multi-cycle signal paths, uninitialized memory arrays, and sequential elements that do not have a back-door access mechanism. Since most large DCCTs have some amount of such circuit elements, they make an expected MISR signature calculated by simulation to contain unknown (or unpredictable) X values, thereby causing the test compression techniques to fail on such DCCTs.
As is well known, a test pattern consists of load, capture and unload procedures applied to a DCCT. Further, the test power of a test pattern is the maximum power dissipated during the load, capture and unload procedures. In a test pattern: (a) after required circuit state values have been shifted into flip-flops (in a load procedure), new values of flip-flops (via their output ports) propagate through the DCCT (via the DCCT logic circuitry) and resultant values appear at data input ports of flip-flops; (b) the resultant values are then clocked into the flip-flops (in a capture procedure); and (c) the stored resultant values are finally shifted out to the DCCT (IC chip) test pins and are compared with expected values (in an unload procedure). As one of ordinary skill in the art can readily appreciate, only a small subset of the flip-flops of a DCCT needs to be loaded or unloaded for a typical test pattern. Thus, all prior art RAS DFT techniques reduce power dissipation during load and unload procedures when compared to serial scan DFT techniques since only the subset of flip-flops that need to be loaded or unloaded are operated using the RAS DFT mechanism. However, power reduction during capture procedures has not been addressed in prior art RAS DFT techniques to date.
Test application time (“TAT”) and test pattern data volume (“TDV”) of prior art SS DFT techniques for DCCTs have been improved by adding scan output compression and scan input decompression logic circuitry to the DCCT. This is illustrated in FIG. 6. In accordance with this improvement, scan input data is compressed a-priori by an ATPG tool to reduce the test pattern data volume. The compressed test stimulus data is decompressed using on-chip decompressors. Further, the response data is compressed on-chip and only the compressed responses are compared with the expected compressed responses calculated by the ATPG tool. Only a small fraction of all flip-flops need to be controlled or observed in each test pattern. So, only a few scan pins can be interfaced to a large number of short serial scan chains to reduce TAT since shorter chains require a smaller number of clock cycles for shifting. However, adverse effects of high test power are still present in such prior art compressed scan (“CS”) DFT techniques since all scan cells are still clocked during load and unload procedures.
As seen from the above, prior art SS DFT techniques suffer from high test application time (“TAT”), high test pattern data volume (“TDV”) and excessive test power (“TP”). In addition, prior art RAS DFT techniques suffer from high routing area overhead. In further addition, prior art CS DFT techniques suffer from high test power (TP).